CA ( CODE:BTCS 301)- 10 MARKS QUESTIONS (NOTES 1)- IMPORTANT & EXPECTED QUESTIONS( IMPORTANT FOR PTU)
COMPUTER ARCHITECTURE ( CODE:BTCS 301)
(IMPORTANT & EXPECTED QUESTIONS-IMPORTANT FOR PTU EXAMS)
QUESTIONS CARRYING 10 MARKS:
Q1. What do you mean by Associative Memory? Explain briefly the hardware organisation of same.
Q2. Write short note on: (a) Vector processors, (b) Instruction Format.
Q3. What do you mean by Instruction Pipeline? Mention the stages of Pipeline.
Q4. What is the difference between Static and Dynamic network interconnections? Discuss any 3 Network interconnection networks.
Q5. Design a 4-bit Arithmatic circuit.
Q6. (a) Give the Flow chart for add and subtract operation of two signed 2's compliment data. Explain the logic of each operation.
(b) Why page table is required in a Virtual Memory system. Explain different ways of organising a page table.
Q7. Explain how Cache memory is different from Virtual memory. Also discuss various page replacement policies for Virtual memory with examples.
Q8. Write short note on: (a) DMA, (b) Stack Organization.
Q9. Explain Instruction Cycle. Give the RTL statement for each sub-cycle. How the Instruction cycle is to accommodate the Interrupt from I/O devices/
Q10. What is Priority Interrupt? Explain Daisy Chaining Priority with diagram.
Q1. What do you mean by Associative Memory? Explain briefly the hardware organisation of same.
Q2. Write short note on: (a) Vector processors, (b) Instruction Format.
Q3. What do you mean by Instruction Pipeline? Mention the stages of Pipeline.
Q4. What is the difference between Static and Dynamic network interconnections? Discuss any 3 Network interconnection networks.
Q5. Design a 4-bit Arithmatic circuit.
Q6. (a) Give the Flow chart for add and subtract operation of two signed 2's compliment data. Explain the logic of each operation.
(b) Why page table is required in a Virtual Memory system. Explain different ways of organising a page table.
Q7. Explain how Cache memory is different from Virtual memory. Also discuss various page replacement policies for Virtual memory with examples.
Q8. Write short note on: (a) DMA, (b) Stack Organization.
Q9. Explain Instruction Cycle. Give the RTL statement for each sub-cycle. How the Instruction cycle is to accommodate the Interrupt from I/O devices/
Q10. What is Priority Interrupt? Explain Daisy Chaining Priority with diagram.
Comments
Post a Comment